An SSD doesn't "spin": it stores information as electrical charges trapped in billions of NAND memory cells. No moving parts, so no mechanical failure — but sophisticated electronics and complex firmware that can fail. Understanding this architecture means understanding why deleted data sometimes vanishes in minutes, and why a "dead" SSD has often lost none of its content.
This chapter grounds the SSD part of the Manual. The SSD chapter of the Guide describes the recovery method; here, the matter it acts upon.
1 · The NAND cell: storing a bit in a charge
The basic unit is the floating-gate transistor: an isolated gate that holds electrons. The amount of trapped charge sets a voltage level, hence a value. Depending on how many levels each cell distinguishes:
- SLC (1 bit/cell) — fast, durable, expensive. Professional use.
- MLC (2 bits) — the historical compromise.
- TLC (3 bits) — today's consumer standard.
- QLC (4 bits) — very dense, less durable.
The more bits per cell, the closer the voltage levels — so the more sensitive reading is to wear. To gain capacity without shrinking the process further, makers stack cells vertically: this is 3D NAND, now exceeding 200 layers.
2 · Pages, blocks and the erase rule
Cells are grouped into pages (the read/write unit), themselves grouped into blocks (the erase unit). A fundamental NAND quirk: you write page by page, but you can only erase whole blocks. A page can't be modified in place: you must rewrite elsewhere and mark the old page obsolete. This asymmetry explains almost all of an SSD firmware's complexity.
3 · The controller and the FTL — the SSD's brain
The controller (Phison, Silicon Motion, Marvell, Samsung…) hides this complexity from the operating system. Its keystone is the FTL (Flash Translation Layer): a table mapping each logical address (LBA) requested by the computer to the real physical location in the NAND. Because data moves constantly, the FTL is volatile and constantly rewritten.
4 · Wear leveling, garbage collection and TRIM
Each cell tolerates a limited number of write/erase cycles. Three mechanisms manage this wear:
- Wear leveling — spreads writes across the device to wear cells evenly.
- Garbage collection — reclaims obsolete pages in the background to free blocks.
- TRIM — a command from the OS marking free blocks, which the SSD then physically erases.
5 · ECC, Bit Rot and threshold reads
Because voltage levels drift with time and wear, each page carries an error-correcting code (ECC), today of the LDPC type. When wear exceeds the correction capacity — the Bit Rot phenomenon — errors become massive. The lab then reads the cells by dynamically shifting the voltage thresholds (Read Retry) and applies soft LDPC decoding to reconstruct the original bits.
6 · Hardware encryption & soldered SSDs
Many SSDs encrypt data on the fly (AES built into the controller). On modern Macs, the SSD is soldered to the board and married to the processor via the Secure Enclave (T2 chips, Apple Silicon M1 to M4): the NAND chips can't be usefully read without the original chain of trust. Recovery then goes through a component-level repair and a hardware DFU read, with decryption only possible with a working Secure Enclave and the key.
7 · Failure map
- FTL / controller (0 GB, SATAFIRM, Busy) → Safe Mode, reverse FTL. ~82%.
- Worn NAND (Bit Rot, slowdowns) → Read Retry, LDPC. Variable.
- Dead controller (drop, surge) → chip-off + reconstruction. 50–70%.
- Soldered Apple SSD → board-level + DFU + decryption. ~80%.
- TRIM fired / secure erase → often irreversible. Low.
SSD recovery is therefore never "mechanical": it's a job of electronics, cryptography and software reconstruction. It's also why the right reflex — cutting power — matters even more than on a hard drive.